1. Field of the Invention
The present invention relates to generating a cell library which stores various kinds of cell data usable for logic design of semiconductor integrated circuits (ICs), and more particularly, to generating a cell library for use in logic simulation of such designed ICs.
2. Description of the Related Art
A net description model and a truth table model are typically used to represent various cells which are used in the logic design stage of semiconductor ICs. In the net description model, cells are defined by elements to be used and net information which connects those elements to one another. In the truth table model, the function of each cell is expressed by a pattern of input signals and corresponding output signals.
Logic simulation is performed on a designed logic circuit to check whether the general operation of the logic circuit yields results that are consistent with expected values. To support proper simulation, when a designed logic circuit includes cells of a truth table model, the truth table model should not include any signal expression which a logic simulator cannot accommodate.
For example, in general, a logic simulator can handle only level signals having values of "0", "1" and "X" (0 or 1) as input signals to cells which constitute a logic circuit. However, typically the expressions of input signals in a truth table model include not only level signals of "0" and "1" but also edge signals, which shows a change in a signal value, i.e., a rising edge and a falling edge. For instance, an edge-signal in a truth table model might correspond to a flip-flop which has a memory function. The expressions of a truth table model corresponding to such a flip-flop include an expression such that for a new input signal value, the signal value of at least one output pin is based on the previous output value.
Therefore, a cell designer typically manually rewrites the edge signals of a truth table model as level signals. At that time, the cell designer would also need to manually add a memory function.
In addition, when a truth table model which refers to a previous output value is present, the cell designer must manually rewrite the truth table model in order to clearly show a memory for holding the previous output value.
Because the aforementioned rewriting of a truth table model is performed manually, this task demands a considerable amount of time and effort of the cell designer. Moreover, the manual rewriting process of the truth table model is likely to contain errors.